收藏本站
of transfers as specified by the channel descriptor (2 ). The USARTs are additionally connected to the
and this determines the arbitration rate. For example, if R = 4 then the arbitration rate is 2 , that is, the
...the world's most energy friendly microcontrollers
off-loading the processor from copying large amounts of data or avoiding frequent interrupts to service
peripherals needing more data or having available data. It can also be used to reduce the system energy
consumption by making the DMA work autonomously with the LEUART for data transfer in EM2 without
having to wake up the processor core from sleep.
The DMA Controller contains 8 independent channels. Each of these channels can be connected to any
of the available peripheral trigger sources by writing to the configuration registers, see Section 8.4.1 (p.
40) . In addition, each channel can be triggered by software (for large memory transfers or for
debugging purposes).
What the DMA Controller should do when one of its channels is triggered, is configured through channel
descriptors residing in system memory. Before enabling a channel, the software must therefore take care
to write this configuration to memory. When the channel is triggered, the DMA Controller will first read
the channel descriptor from system memory, and then it will proceed to perform the memory transfers
as specified by the descriptor. The descriptor contains the memory address to read from, the memory
address to write to, the number of bytes to be transferred, etc. The channel descriptor is described in
detail in Section 8.4.3 (p. 50) .
In addition to the basic transfer mode, the DMA Controller also supports two advanced transfer modes;
ping-pong and scatter-gather. Ping-pong transfers are ideally suited for streaming data for high-speed
peripheral communication as the DMA will be ready to retrieve the next incoming data bytes immediately
while the processor core is still processing the previous ones (and similarly for outgoing communication).
Scatter-gather involves executing a series of tasks from memory, and allows sophisticated schemes to
be implemented by software.
Using different priority levels for the channels and setting the number of bytes after which the DMA
Controller rearbitrates, it is possible to ensure that timing-critical transfers are serviced on time.
8.4.1 Channel Select Configuration
The channel select block allows selecting which peripheral's request lines (dma_req, dma_sreq) to
connect to each DMA channel.
This configuration is done by software through the extra registers DMA_CH0_CTRL- DMA_CH7_CTRL,
with SOURCESEL and SIGSEL components. SOURCESEL selects which peripheral to listen to.
SIGSEL selects which of the peripheral’s output signals is selected.
All peripherals are connected to dma_req. When this signal is triggered, the DMA performs a number
R
dma_sreq line. When only dma_sreq is asserted but not dma_req, then the DMA will perform exactly
one transfer only (given that dma_sreq is enabled by software).
8.4.2 DMA control
8.4.2.1 DMA arbitration rate
You can configure when the controller arbitrates during a DMA transfer. This enables you to reduce the
latency to service a higher priority channel.
The controller provides four bits that configure how many AHB bus transfers occur before it rearbitrates.
These bits are known as the R_power bits because the value you enter, R, is raised to the power of two
4
controller arbitrates every 16 DMA transfers.
Table 8.1 (p. 40) lists the arbitration rates.
Table 8.1. AHB bus transfer arbitration interval
R_power
b0000
Arbitrate after x DMA transfers
x=1
2011-04-12 - d0001_Rev1.10
40
www.energymicro.com
发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

*型号 *数量 厂商 批号 封装
添加更多采购

我的联系方式

*
*
*
相关PDF资料
EFM32GG-STK3700 KIT STARTER GIANT GECKO
EFM32LG-DK3650 KIT DEV EFM32 LEOPARD GECKO
EK-K7-KC705-CES-G-J KINTEX-7 FPGA KC705 EVAL KIT
EK-S6-SP601-G KIT EVAL SPARTAN 6 SP601
EK-S6-SP605-G KIT EVAL SPARTAN 6 SP605
EK-V6-ML631-G-J VIRTEX-6 HXT FPGA ML631 EVAL KIT
EK-V7-VC707-CES-G VIRTEX-7 VC707 EVAL KIT
EK-Z7-ZC702-CES-G ZYNQ-7000 EPP ZC702 EVAL KIT
相关代理商/技术参数
EFM32GG230F1024 功能描述:ARM微控制器 - MCU 1024KB FL 128KB RAM RoHS:否 制造商:STMicroelectronics 核心:ARM Cortex M4F 处理器系列:STM32F373xx 数据总线宽度:32 bit 最大时钟频率:72 MHz 程序存储器大小:256 KB 数据 RAM 大小:32 KB 片上 ADC:Yes 工作电源电压:1.65 V to 3.6 V, 2 V to 3.6 V, 2.2 V to 3.6 V 工作温度范围:- 40 C to + 85 C 封装 / 箱体:LQFP-48 安装风格:SMD/SMT
EFM32GG230F1024G-E-QFN64R 功能描述:IC MCU 32BIT 1MB FLASH 64QFN 制造商:silicon labs 系列:Giant Gecko 包装:剪切带（CT） 零件状态:在售 核心处理器:ARM? Cortex?-M3 核心尺寸:32-位 速度:48MHz 连接性:I2C，IrDA，智能卡，SPI，UART/USART 外设:欠压检测/复位，DMA，POR，PWM，WDT I/O 数:56 程序存储容量:1MB（1M x 8） 程序存储器类型:闪存 EEPROM 容量:- RAM 容量:128K x 8 电压 - 电源（Vcc/Vdd）:1.98 V ~ 3.8 V 数据转换器:A/D 8x12b，D/A 2x12b 振荡器类型:内部 工作温度:-40°C ~ 85°C（TA） 封装/外壳:64-VFQFN 裸露焊盘 供应商器件封装:64-QFN（9x9） 标准包装:1
EFM32GG230F1024-QFN64 制造商:Energy Micro AS 功能描述:GIANT GECKO MCU - Cut TR (SOS) 制造商:Energy Micro 功能描述:GIANT GECKO MCU 制造商:Energy Micro AS 功能描述:IC MCU 32BIT 1MB FLASH 64QFN
EFM32GG230F1024-QFN64T 制造商:Energy Micro AS 功能描述:GIANT GECKO MCU - Trays
EFM32GG230F1024-QFN64-T 制造商:Energy Micro AS 功能描述:IC MCU 32BIT 1MB FLASH 64QFN
EFM32-GG230F1024-SK 制造商:Energy Micro AS 功能描述:GIANT GECKO SAMPLE KIT - Bulk
EFM32GG230F1024-T 制造商:Energy Micro AS 功能描述:IC MCU 32BIT 1MB FLASH 64QFN
EFM32GG230F512 功能描述:ARM微控制器 - MCU 512KB FL 128KB RAM RoHS:否 制造商:STMicroelectronics 核心:ARM Cortex M4F 处理器系列:STM32F373xx 数据总线宽度:32 bit 最大时钟频率:72 MHz 程序存储器大小:256 KB 数据 RAM 大小:32 KB 片上 ADC:Yes 工作电源电压:1.65 V to 3.6 V, 2 V to 3.6 V, 2.2 V to 3.6 V 工作温度范围:- 40 C to + 85 C 封装 / 箱体:LQFP-48 安装风格:SMD/SMT